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|Título:||Performance comparison of parallel architectures for real-time control|
|Autor:||Daniel, H. A.|
Ruano, A. E.
Heterogeneous parallel architectures
Digital signal processors
|Citação:||Daniel, H. A.; Ruano, A. E. B. Performance comparison of parallel architectures for real-time control, Microprocessors and Microsystems, 23, 6, 325-336, 1999.|
|Resumo:||In this paper the performance of several parallel architectures for the implementation of matrix-intensive control algorithms is compared. To investigate their performance, a parallel version of an Adaptive Generalized Predictive Control algorithm (AGPC) is mapped over these architectures. Since this algorithm needs to be fed with the knowledge of the plant transfer function, the parallelization of a standard Recursive Least Squares (RLS) estimator and of a GPC predictor is discussed here. The former step operates over a small set of data, while the latter uses a larger set of data, therefore making this algorithm a valid benchmark to measure the performance of such architectures for these two different situations. Two homogeneous architectures built of T805 transputers and TMS320C40 DSPs are investigated. Also two different networks built of T805 and TMS320C40 are used to measure the performance of heterogeneous architectures. Execution times and efficiency results of the RLS and GPC steps presented illustrate that the TMS320C40 network is the fastest network tested. However, for low complexity algorithms, depending on the sampling time, even the slow transputer homogeneous architecture may still have the required performance. In the general case, there is no benefit in using both heterogeneous architectures tested, since they cannot outperform the TMS320C40 homogeneous architectures. (C) 1999 Elsevier Science B.V. All rights reserved.|
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