Kiazadeh, AsalGomes, Henrique L.Barquinha, PedroMartins, JorgeRovisco, AnaPinto, Joana V.Martins, RodrigoFortunato, Elvira2017-04-072017-04-072016-080003-6951AUT: HGO00803;http://hdl.handle.net/10400.1/9363The impact of a parylene top-coating layer on the illumination and bias stress instabilities of indium-gallium-zinc oxide thin-film transistors (TFTs) is presented and discussed. The parylene coating substantially reduces the threshold voltage shift caused by continuous application of a gate bias and light exposure. The operational stability improves by 75%, and the light induced instability is reduced by 35%. The operational stability is quantified by fitting the threshold voltage shift with a stretched exponential model. Storage time as long as 7 months does not cause any measurable degradation on the electrical performance. It is proposed that parylene plays not only the role of an encapsulation layer but also of a defect passivation on the top semiconductor surface. It is also reported that depletion-mode TFTs are less sensitive to light induced instabilities. This is attributed to a defect neutralization process in the presence of free electrons. Published by AIP Publishing.engjournal article10.1063/1.4960200