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Performance comparison of parallel architectures for real-time control

dc.contributor.authorDaniel, H. A.
dc.contributor.authorRuano, Antonio
dc.date.accessioned2013-02-02T12:36:07Z
dc.date.available2013-02-02T12:36:07Z
dc.date.issued1999
dc.date.updated2013-01-28T09:53:58Z
dc.description.abstractIn this paper the performance of several parallel architectures for the implementation of matrix-intensive control algorithms is compared. To investigate their performance, a parallel version of an Adaptive Generalized Predictive Control algorithm (AGPC) is mapped over these architectures. Since this algorithm needs to be fed with the knowledge of the plant transfer function, the parallelization of a standard Recursive Least Squares (RLS) estimator and of a GPC predictor is discussed here. The former step operates over a small set of data, while the latter uses a larger set of data, therefore making this algorithm a valid benchmark to measure the performance of such architectures for these two different situations. Two homogeneous architectures built of T805 transputers and TMS320C40 DSPs are investigated. Also two different networks built of T805 and TMS320C40 are used to measure the performance of heterogeneous architectures. Execution times and efficiency results of the RLS and GPC steps presented illustrate that the TMS320C40 network is the fastest network tested. However, for low complexity algorithms, depending on the sampling time, even the slow transputer homogeneous architecture may still have the required performance. In the general case, there is no benefit in using both heterogeneous architectures tested, since they cannot outperform the TMS320C40 homogeneous architectures. (C) 1999 Elsevier Science B.V. All rights reserved.
dc.identifier.citationDaniel, H. A.; Ruano, A. E. B. Performance comparison of parallel architectures for real-time control, Microprocessors and Microsystems, 23, 6, 325-336, 1999.por
dc.identifier.doi10.1016/S0141-9331(99)00040-X
dc.identifier.issn01419331
dc.identifier.issn0141-9331
dc.identifier.otherAUT: HDA01050; ARU00698;
dc.identifier.urihttp://hdl.handle.net/10400.1/2198
dc.language.isoengpor
dc.peerreviewedyespor
dc.publisherElsevierpor
dc.subjectReal-time controlpor
dc.subjectAdaptive controlpor
dc.subjectMultiprocessors systemspor
dc.subjectHeterogeneous parallel architecturespor
dc.subjectDigital signal processorspor
dc.titlePerformance comparison of parallel architectures for real-time controlpor
dc.typejournal article
dspace.entity.typePublication
oaire.citation.endPage336por
oaire.citation.issue6por
oaire.citation.startPage325por
oaire.citation.titleMicroprocessors and Microsystemspor
oaire.citation.volume23por
person.familyNameRuano
person.givenNameAntonio
person.identifier.orcid0000-0002-6308-8666
person.identifier.ridB-4135-2008
person.identifier.scopus-author-id7004284159
rcaap.rightsopenAccesspor
rcaap.typearticlepor
relation.isAuthorOfPublication13813664-b68b-40aa-97a9-91481a31ebf2
relation.isAuthorOfPublication.latestForDiscovery13813664-b68b-40aa-97a9-91481a31ebf2

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