Publication
Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGA
| dc.contributor.author | Perina, Andre Bannwart | |
| dc.contributor.author | Matias, Paulo | |
| dc.contributor.author | Marques, Eduardo | |
| dc.contributor.author | Bonato, Vanderlei | |
| dc.contributor.author | Lima, João | |
| dc.contributor.editor | Kubatova, H. | |
| dc.contributor.editor | Novotny, M. | |
| dc.contributor.editor | Skavhaug, A. | |
| dc.date.accessioned | 2019-11-20T15:07:56Z | |
| dc.date.available | 2019-11-20T15:07:56Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | Matrix inversion for real-time applications can be a challenge for the designers since its computational complexity is typically cubic. Parallelism has been widely exploited to reduce such complexity, however most traditional methods do not scale well with the matrix size leading to communication bottlenecks. In this paper we exploit a decentralised parallel hardware architecture based on a strongly non-singular matrix inversion algorithm proposed by Kant and Kimura in 1978, which is a parallel-orientated method with communication mode independent of the matrix size, mitigating the problem of matrix scalability. The hardware architecture is implemented in two different approaches using fixed-point arithmetic: dedicated and shared. In the first approach a matrix can be inverted in linear time while the latter, for the best case, has a square complexity. Experimental results are demonstrated using a Stratix V GX FPGA. For instance, in dedicated approach an 8x8 matrix is inverted in 1.27us, while in shared approach a 64x64 matrix is inverted in 153.40us using 64 pipelined processing elements. | |
| dc.description.sponsorship | FAPESP (Sao Paulo Research Foundation) | |
| dc.identifier.doi | 10.1109/DSD.2017.32 | |
| dc.identifier.isbn | 978-1-5386-2146-2 | |
| dc.identifier.uri | http://hdl.handle.net/10400.1/13283 | |
| dc.language.iso | eng | |
| dc.peerreviewed | yes | |
| dc.publisher | IEEE | |
| dc.title | Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGA | |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.citation.conferencePlace | Vienna, Austria | |
| oaire.citation.endPage | 519 | |
| oaire.citation.startPage | 516 | |
| oaire.citation.title | 2017 Euromicro Conference on Digital System Design (Dsd) | |
| oaire.citation.title | 20th Euromicro Conference on Digital System Design (Dsd) | |
| person.familyName | Lima | |
| person.givenName | João | |
| person.identifier.ciencia-id | F319-672D-5416 | |
| person.identifier.orcid | 0000-0003-3561-4267 | |
| rcaap.rights | restrictedAccess | |
| rcaap.type | conferenceObject | |
| relation.isAuthorOfPublication | d96029c0-7218-497d-978c-fc61b85d1fb2 | |
| relation.isAuthorOfPublication.latestForDiscovery | d96029c0-7218-497d-978c-fc61b85d1fb2 |
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